3-Week Verilog HDL Course Content

Duration: 3 Weeks
Mode: Online / Offline
Level: Beginner to Intermediate

Course Overview

This 3-Week Verilog HDL Course introduces students to digital system design using Verilog. The course focuses on core concepts, practical coding, simulation, and verification, helping learners gain hands-on experience with industry-relevant design techniques.

Learning Outcomes

After completing the course, students will be able to:

• Understand digital design and Verilog fundamentals

• Write synthesizable Verilog code

• Design combinational and sequential circuits

• Create testbenches for simulation

• Implement a basic Verilog mini project

Week 1: Verilog Basics & Combinational Logic

Topics Covered

• Introduction to Digital Electronics

• Number Systems and Logic Gates

• Introduction to HDL and Verilog

• Structure of Verilog Programs

• Modules and Ports

• Data Types: wire, reg, parameter

• Operators in Verilog

• Continuous Assignments (assign)

• Combinational Logic Design

Practical Sessions

• Half Adder

• Full Adder

• Multiplexer

• Decoder

Week 2: Sequential Logic & Behavioral Modeling

Topics Covered

• Procedural Blocks: always, initial

• Blocking vs Non-Blocking Assignments

• Sensitivity Lists

• Conditional Statements (if-else, case)

• Latches and Flip-Flops

• Counters and Registers

• Clock and Reset Concepts

Practical Sessions

• D Flip-Flop

• Up Counter / Down Counter

• Shift Register

• Register Design

Week 3: FSM, Testbenches & Mini Project

Topics Covered

• Introduction to Finite State Machines (FSM)

• Moore and Mealy FSM

• FSM Coding Style in Verilog

• Introduction to Testbenches

• Writing Testbench Stimulus

• Timing Control and Delays

• Simulation and Debugging

• Synthesizable Coding Guidelines

Mini Project (Any One)

• Traffic Light Controller

• 4-bit ALU

• Digital Stopwatch

• Vending Machine Controller

Tools & Software

• ModelSim / QuestaSim

• Xilinx Vivado

• GTKWave

Certification

• Certificate of Completion provided after successful project submission