Verilog HDL 2-Week

📌 Course Overview

This 2-Week Verilog HDL Course introduces learners to Hardware Description Language (HDL) used in digital circuit design and VLSI systems. The course focuses on concept clarity, coding practice, and simulation, making it ideal for beginners and engineering students.

🎯 Course Objectives

• Understand the basics of Verilog HDL

• Learn digital design using Verilog

• Write synthesizable Verilog code

• Simulate and test digital circuits

• Prepare for VLSI, FPGA, and core electronics roles

🗓️ Course Duration

2 Weeks (Online / Offline / Hybrid)

📘 Week-Wise Course Content

🔹 Week 1: Verilog Basics & Combinational Logic

• Introduction to Verilog HDL

• Verilog vs VHDL

• Digital Design Flow

• Structure of a Verilog Program

• Data Types (wire, reg, integer)

• Operators in Verilog

• Modules & Ports

• Continuous Assignments

• Always Blocks (Basics)

• Combinational Logic Design

  • AND, OR, NOT, XOR

  • Multiplexer

  • Decoder & Encoder

✅ Assignment (Week-1):
Write Verilog code for basic combinational circuits and simulate them.

🔹 Week 2: Sequential Logic & Simulation

• Sequential Circuits Overview

• Flip-Flops (D, JK, T) using Verilog

• Registers & Counters

• Clock & Reset Concepts

• Blocking vs Non-Blocking Assignments

• Testbench Writing

• Simulation using ModelSim / Vivado (Intro)

• Common Coding Mistakes

• Introduction to FPGA & VLSI Flow

• Real-World Applications of Verilog

✅ Final Mini Project:

• Design a 4-bit Counter / ALU / FSM