Verilog HDL 4-Week

This 4-Week Verilog HDL Course is designed to build strong foundations in digital system design and hardware description using Verilog. The course focuses on hands-on coding, simulation, debugging, and real-world design practices used in VLSI and FPGA industries.

By the end of the course, learners will be able to design, simulate, and verify digital circuits using industry-standard Verilog coding techniques and complete a realistic mini project.

Learning Outcomes

After completing this course, students will be able to:

• Understand digital design concepts and HDL fundamentals

• Write synthesizable Verilog code

• Design combinational and sequential circuits

• Implement and verify FSM-based systems

• Develop Verilog testbenches for simulation

• Understand synthesis and FPGA design flow

• Complete an industry-oriented mini project

Week 1: Digital Design & Verilog Fundamentals

Concepts Covered

• Introduction to Digital Electronics

• Number Systems (Binary, Decimal, Hexadecimal)

• Logic Gates and Boolean Algebra

• Introduction to HDL (Why Verilog?)

• Difference between Verilog & VHDL

• Structure of a Verilog Program

• Modules and Ports

• Data Types: wire, reg, parameter

• Operators in Verilog (Arithmetic, Logical, Relational, Bitwise)

Hands-On Practice

• Writing basic Verilog modules

• Continuous assignment (assign)

• Design of:

  • Half Adder

  • Full Adder

  • Multiplexer

  • Decoder

Tools

• ModelSim / Vivado Simulation

• Understanding waveform analysis

Week 2: Combinational & Sequential Logic Design

Concepts Covered

• Procedural Blocks: always, initial

• Blocking vs Non-Blocking Assignments

• Sensitivity Lists

• Conditional Statements (if-else)

• case, casex, casez

• Combinational vs Sequential Logic

• Latches and Flip-Flops

• Clock and Reset Concepts

Hands-On Practice

• D Flip-Flop

• JK Flip-Flop

• Shift Registers

• Counters (Up, Down, Up/Down)

• Register Design

Simulation

• Clock generation

• Reset behavior testing

Week 3: FSM, Testbenches & Verification

Concepts Covered

• Introduction to Finite State Machines (FSM)

• Moore and Mealy FSM

• FSM State Encoding

• Writing FSM in Verilog

• Introduction to Testbenches

• Writing stimulus and monitoring outputs

• Tasks and Functions

• Timing Control and Delays

• timescale directive

Hands-On Practice

• FSM-based designs

• Self-checking testbenches

• Debugging logic using waveform viewers

Week 4: Synthesis, FPGA Flow & Mini Project

Concepts Covered

• Synthesizable vs Non-Synthesizable Code

• RTL Design Guidelines

• Common Verilog Coding Mistakes

• Introduction to FPGA Architecture

• FPGA Design Flow:

  • RTL Design

  • Simulation

  • Synthesis

  • Implementation

• Constraints Overview

Mini Project (Any One)

• Traffic Light Controller using FSM

• 4-bit ALU Design

• Digital Stopwatch

• Vending Machine Controller

• UART Transmitter (Basic)

Project Deliverables

• Verilog Source Code

• Testbench

• Simulation Waveforms

• Project Explanation

Tools & Software Used

• ModelSim / QuestaSim

• Xilinx Vivado

• GTKWave

• Any Verilog-compatible simulator